CMOS circuits offer two main advantages over circuits manufactured in accordance with the single-channel technology:
(1) Their standby power dissipation is mostly negligibly small because it is only caused by inverse currents.
(2) They are capable of providing at the output a very-low ohmic voltage source for operating a useful load.
These two advantages add towards the fact that CMOS circuits can be preferably used also with higher operating voltages. The power dissipation of the output transistors operating in a source circuit can be kept very small and almost independent of the voltage, by a large W/L ratio also under load conditions.
The drive power Pg, as required at the gate electrodes of the output transistors, increases as the square of the increasing operating voltage U.sub.B, and, especially in the case of a high gate capacity EQU Cg=W.multidot.L.multidot.Cox
with W=channel width, L=channel length, Cox=specific capacity, and at a high frequency f, may have disturbing effects: EQU Pg=f Cg U.sub.B.sup.2.
This drive power also appears when at the output there is not required a useful power, but merely a high voltage. This, for example, applies to the case of a peripheral circuit for the programming of nonvolatile storing field-effect memory transistors of a storage matrix, as is known, for example, from the European Patent Application (EP-OS) No. 00 20 054.
In the case of such a storage matrix, the drive power required for the programming is distributed to a plurality of transistors. In the case of a 16k-matrix storage employing n-channel floatinggate cells, organized in 128 rows and 128 columns, there will probably be concerned e.g., 128 switching transistors whose gate electrodes have to be momentarily switched to a programming voltage of about 20 V.